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K60P100M100SF2RM Datasheet, PDF (906/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual | |||
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Introduction
⢠Optional back-to-back mode operation, which enables the ADC conversions
complete to trigger the next PDB channel
⢠One programmable delay interrupt
⢠One sequence error interrupt
⢠One channel flag and one sequence error flag per pre-trigger
⢠DMA support
⢠Up to eight DAC interval triggers
⢠One interval trigger output per DAC
⢠One 16-bit delay interval register per DAC trigger output
⢠Optional bypass the delay interval trigger registers
⢠Optional external triggers
⢠Up to eight pulse outputs (pulse-out's)
⢠Pulse-out's can be enabled or disabled independently.
⢠Programmable pulse width
NOTE
The number of PDB input and output triggers are chip-specific.
Refer to the Chip Configuration information for details.
38.1.2 Implementation
In this chapter, the following letters refers to the number of output triggers.
⢠N â Total available number of PDB channels.
⢠n â PDB channel number, valid from 0 to N-1.
⢠M â Total available pre-trigger per PDB channel.
⢠m â Pre-trigger number, valid from 0 to M-1.
⢠X â Total number of DAC interval triggers.
⢠x â DAC interval trigger output number, valid from 0 to X-1.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
906
Freescale Semiconductor, Inc.
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