K60P100M100SF2RM Datasheet, PDF (1652/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Initialization/application of SDHC
3. Set the SDHC block length register to be the same as the block length set for the card
in Step 2.
4. Set the SDHC number block register (NOB), nob is 5 (for instance).
5. Disable the buffer read ready interrupt, configure the DMA settings and enable the
SDHC DMA when sending the command with data transfer. The
XFERTYP[AC12EN] bit should also be set:
6. Wait for the transfer complete interrupt.
7. Check the status bit to see if a read CRC error occurred, or some another error,
occurred during the auto12 command sending and response receiving.
52.6.3.2.2 Read with pause
The read operation is not generally able to pause. Only the SDIO card (and SDCombo
card working under I/O mode) supporting the read and wait feature can pause during the
read operation. If the SDIO card support read wait (SRW bit in CCCR register is 1), the
Driver can set the SABGREQ bit in the Protocol Control register to pause the transfer
between the data blocks. Before setting the SABGREQ bit, make sure the RWCTL bit in
the Protocol Control register is set, otherwise the eSDHC will not assert the Read Wait
signal during the block gap and data corruption occurs. It is recommended to set the
RWCTL bit once the Read Wait capability of the SDIO card is recognized.
Like in the flow described in Normal read, the read with pause is shown with the same
kind of read operation:
1. Check the SRW bit in the CCR register on the SDIO card to confirm the card
supports Read Wait.
2. Set the RWCTL bit.
3. Check the card status and wait until the card is ready for data.
4. Set the card block length/size:
a. For SD/MMC, use SET_BLOCKLEN (CMD16)
b. For SDIO cards or the I/O portion of SDCombo cards, use
IO_RW_DIRECT(CMD52) to set the I/O Block Size bit field in the CCCR
register (for function 0) or FBR register (for functions 1~7)
c. For CE-ATA cards, configure bits 1~0 in the scrControl register
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.