K60P100M100SF2RM Datasheet, PDF (979/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
16
HWRSTCNT
15–13
Reserved
12
SWSOC
11
SWINVC
10
SWOM
9
SWWRBUF
8
SWRSTCNT
7
SYNCMODE
6
Reserved
5
SWOC
4
INVC
3
Reserved
2
CNTINC
Chapter 39 FlexTimer (FTM)
FTMx_SYNCONF field descriptions (continued)
Description
FTM counter synchronization is activated by a hardware trigger.
0 A hardware trigger does not activate the FTM counter synchronization.
1 A hardware trigger activates the FTM counter synchronization.
This read-only field is reserved and always has the value zero.
Software output control synchronization is activated by the software trigger.
0 The software trigger does not activate the SWOCTRL register synchronization.
1 The software trigger activates the SWOCTRL register synchronization.
Inverting control synchronization is activated by the software trigger.
0 The software trigger does not activate the INVCTRL register synchronization.
1 The software trigger activates the INVCTRL register synchronization.
Output mask synchronization is activated by the software trigger.
0 The software trigger does not activate the OUTMASK register synchronization.
1 The software trigger activates the OUTMASK register synchronization.
MOD, CNTIN, and CV registers synchronization is activated by the software trigger.
0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
1 The software trigger activates MOD, CNTIN, and CV registers synchronization.
FTM counter synchronization is activated by the software trigger.
0 The software trigger does not activate the FTM counter synchronization.
1 The software trigger activates the FTM counter synchronization.
Synchronization Mode
Selects the PWM synchronization mode.
0 Legacy PWM synchronization is selected.
1 Enhanced PWM synchronization is selected.
This read-only field is reserved and always has the value zero.
SWOCTRL register synchronization
0 SWOCTRL register is updated with its buffer value at all rising edges of system clock.
1 SWOCTRL register is updated with its buffer value by the PWM synchronization.
INVCTRL register synchronization
0 INVCTRL register is updated with its buffer value at all rising edges of system clock.
1 INVCTRL register is updated with its buffer value by the PWM synchronization.
This read-only field is reserved and always has the value zero.
CNTIN register synchronization
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
979