K60P100M100SF2RM Datasheet, PDF (104/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memories and Memory Interfaces
Table 3-36. Reference links to related information (continued)
Topic
Transfers
Transfers
Register access
Related module
MPU
Crossbar switch
Peripheral bridge
Reference
MPU
Crossbar Switch
Peripheral bridge
3.5.2.1 Number of masters
The Flash Memory Controller supports up to eight crossbar switch masters. However,
this device has a different number of crossbar switch masters. See Crossbar Switch
Configuration for details on the master port assignments.
3.5.2.2 Program Flash Swap
On devices that contain program flash memory only, the program flash memory blocks
may swap their base addresses.
While not using swap:
• FMC_PFB0CR controls the lower code addresses (block 0)
• FMC_PFB1CR controls the upper code addresses (block 1)
If swap is used, the opposite is true:
• FMC_PFB0CR controls the upper code addresses (now in block 0)
• FMC_PFB1CR controls the lower code addresses (now in block 1)
3.5.3 SRAM Configuration
This section summarizes how the module has been configured in the chip.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
104
Freescale Semiconductor, Inc.