K60P100M100SF2RM Datasheet, PDF (141/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

3.9.1.2 RMII Clocking
Chapter 3 Chip Configuration
On this device, RMII_REF_CLK is internally tied to EXTAL. See Clock Distribution for
clocking requirements.
3.9.1.3 IEEE 1588 Timers
The ethernet module includes a four channel timer module for IEEE 1588 timestamping.
The timer supports input capture (rising, falling, or both edges), output compare (toggle
or pulse with programmable polarity). The timer matches on greater than or equal (the
1588 can skip numbers, so the counter might not ever exactly match the compare value).
The counter is able to operate asynchronously to the ethernet bus by using one of four
clock sources. See Ethernet Clocking for more details.
3.9.1.4 Ethernet Operation in Low Power Modes
The Ethernet module is not fully operational in any low power modes. However, the
module does support magic packet detection that can generate a wakeup in stop mode if
enabled.
During low power operation:
• The MAC transmit logic is disabled
• The core FIFO receive/transmit functions are disabled
• The MAC receive logic is kept in normal mode, but it ignores all traffic from the line
except magic packets.
The recieve logic needed for magic packet detection is clocked using the externally-
supplied MII or RMII clock. This allows for the wakeup functionality in stop mode. No
Ethernet operation, including magic packet wakeup, is supported in VLPx modes.
3.9.1.4.1 IEEE 1588 Timer Operation in Low Power Modes
The 1588 counter and 1588 timer channels can continue operating in low power modes
provided their clock is enabled in that mode.
The 1588 timer channels can also generate an interrupt to exit the low power mode if the
clock is enabled in that mode.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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