K60P100M100SF2RM Datasheet, PDF (1116/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Register definition
43.2.6 RTC Status Register (RTC_SR)
Address: RTC_SR is 4003_D000h base + 14h offset = 4003_D014h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0 TAF TOF TIF
TCE
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
RTC_SR field descriptions
Field
31–5
Reserved
4
TCE
Description
This read-only field is reserved and always has the value zero.
Time Counter Enable
When time counter is disabled the TSR register and TPR register are writeable, but do not increment.
When time counter is enabled the TSR register and TPR register are not writeable, but increment.
3
Reserved
2
TAF
0 Time counter is disabled.
1 Time counter is enabled.
This read-only field is reserved and always has the value zero.
Time Alarm Flag
Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments. This bit is
cleared by writing the TAR register.
1
TOF
0 Time alarm has not occurred.
1 Time alarm has occurred.
Time Overflow Flag
Time overflow flag is set when the time counter is enabled and overflows. The TSR and TPR do not
increment and read as zero when this bit is set. This bit is cleared by writing the TSR register when the
time counter is disabled.
0 Time overflow has not occurred.
1 Time overflow has occurred and time counter is read as zero.
0
Time Invalid Flag
TIF
The time invalid flag is set on VBAT POR or software reset. The TSR and TPR do not increment and read
as zero when this bit is set. This bit is cleared by writing the TSR register when the time counter is
disabled.
0 Time is valid.
1 Time is invalid and time counter is read as zero.
1116
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.