K60P100M100SF2RM Datasheet, PDF (1415/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 49 SPI (DSPI)
49.3.8 DSPI PUSH TX FIFO Register In Slave Mode
(SPIx_PUSHR_SLAVE)
PUSHR provides the means to write to the TX FIFO. Data written to this register is
transferred to the TX FIFO. Eight- or sixteen-bit write accesses to the PUSHR transfer all
32 register bits to the TX FIFO. The register structure is different in master and slave
modes. In master mode the register provides 16-bit command and 16-bit data to the TX
FIFO. In slave mode all 32 register bits can be used as data, supporting up to 32-bit SPI
frame operation.
Addresses: SPI0_PUSHR_SLAVE is 4002_C000h base + 34h offset = 4002_C034h
SPI1_PUSHR_SLAVE is 4002_D000h base + 34h offset = 4002_D034h
SPI2_PUSHR_SLAVE is 400A_C000h base + 34h offset = 400A_C034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_PUSHR_SLAVE field descriptions
Field
31–0
TXDATA
Transmit Data
Description
Holds SPI data to be transferred according to the associated SPI command.
49.3.9 DSPI POP RX FIFO Register (SPIx_POPR)
POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the POPR have
the same effect on the RX FIFO as 32-bit read accesses. A write to this register will
generate a Transfer Error.
Addresses: SPI0_POPR is 4002_C000h base + 38h offset = 4002_C038h
SPI1_POPR is 4002_D000h base + 38h offset = 4002_D038h
SPI2_POPR is 400A_C000h base + 38h offset = 400A_C038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1415