K60P100M100SF2RM Datasheet, PDF (1369/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 48 CAN (FlexCAN)
• MCR[AEN] bit must be asserted;
• the first CPU action must be the writing of abort code (0b1001) into the CODE field
of the Control and Status word.
The active MBs configured as transmission must be aborted first and then they may be
updated. If the abort code is written to a Mailbox that is currently being transmitted, or to
a Mailbox that was already loaded into the SMB for transmission, the write operation is
blocked and the MB is kept active, but the abort request is captured and kept pending
until one of the following conditions are satisfied:
• The module loses the bus arbitration
• There is an error during the transmission
• The module is put into Freeze Mode
• The module enters in BusOff state
• There is an overload frame
If none of conditions above are reached, the MB is transmitted correctly, the interrupt
flag is set in the IFLAG register and an interrupt to the CPU is generated (if enabled).
The abort request is automatically cleared when the interrupt flag is set. On the other
hand, if one of the above conditions is reached, the frame is not transmitted; therefore, the
abort code is written into the CODE field, the interrupt flag is set in the IFLAG and an
interrupt is (optionally) generated to the CPU.
If the CPU writes the abort code before the transmission begins internally, then the write
operation is not blocked; therefore, the MB is updated and the interrupt flag is set. In this
way the CPU just needs to read the abort code to make sure the active MB was safely
inactivated. Although the AEN bit is asserted and the CPU wrote the abort code, in this
case the MB is inactivated and not aborted, because the transmission did not start yet.
One Mailbox is only aborted when the abort request is captured and kept pending until
one of the previous conditions are satisfied.
The abort procedure can be summarized as follows:
• CPU checks the corresponding IFLAG and clears it, if asserted.
• CPU writes 0b1001 into the CODE field of the C/S word.
• CPU waits for the corresponding IFLAG indicating that the frame was either
transmitted or aborted.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1369