K60P100M100SF2RM Datasheet, PDF (1140/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
ENET_EIMR field descriptions (continued)
Field
24
RXB
23
MII
22
EBERR
21
LC
20
RL
19
UN
18
PLR
17
WAKEUP
Description
interrupting source. The corresponding EIR RXF bit reflects the state of the interrupt signal even if the
corresponding EIMR bit is cleared.
RXB interrupt mask
Corresponds to interrupt source RXB defined by the EIR register and determines whether an interrupt
condition can generate an interrupt. At every module clock, the EIR samples the signal generated by the
interrupting source. The corresponding EIR RXB bit reflects the state of the interrupt signal even if the
corresponding EIMR bit is cleared.
MII interrupt mask
Corresponds to interrupt source MII defined by the EIR register and determines whether an interrupt
condition can generate an interrupt. At every module clock, the EIR samples the signal generated by the
interrupting source. The corresponding EIR MII bit reflects the state of the interrupt signal even if the
corresponding EIMR bit is cleared.
EBERR interrupt mask
Corresponds to interrupt source EBERR defined by the EIR register and determines whether an interrupt
condition can generate an interrupt. At every module clock, the EIR samples the signal generated by the
interrupting source. The corresponding EIR EBERR bit reflects the state of the interrupt signal even if the
corresponding EIMR bit is cleared.
LC interrupt mask
Corresponds to interrupt source LC defined by the EIR register and determines whether an interrupt
condition can generate an interrupt. At every module clock, the EIR samples the signal generated by the
interrupting source. The corresponding EIR LC bit reflects the state of the interrupt signal even if the
corresponding EIMR bit is cleared.
RL interrupt mask
Corresponds to interrupt source RL defined by the EIR register and determines whether an interrupt
condition can generate an interrupt. At every module clock, the EIR samples the signal generated by the
interrupting source. The corresponding EIR RL bit reflects the state of the interrupt signal even if the
corresponding EIMR bit is cleared.
UN interrupt mask
Corresponds to interrupt source UN defined by the EIR register and determines whether an interrupt
condition can generate an interrupt. At every module clock, the EIR samples the signal generated by the
interrupting source. The corresponding EIR UN bit reflects the state of the interrupt signal even if the
corresponding EIMR bit is cleared.
PLR interrupt mask
Corresponds to interrupt source PLR defined by the EIR register and determines whether an interrupt
condition can generate an interrupt. At every module clock, the EIR samples the signal generated by the
interrupting source. The corresponding EIR PLR bit reflects the state of the interrupt signal even if the
corresponding EIMR bit is cleared.
WAKEUP interrupt mask
Corresponds to interrupt source WAKEUP defined by the EIR register and determines whether an
interrupt condition can generate an interrupt. At every module clock, the EIR samples the signal
generated by the interrupting source. The corresponding EIR WAKEUP bit reflects the state of the
interrupt signal even if the corresponding EIMR bit is cleared.
Table continues on the next page...
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.