K60P100M100SF2RM Datasheet, PDF (1064/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Signal Description
Peripheral
Bus
PIT
PIT
Registers
Iinterrupts
Triggers
load_value
Timer 1
Peripheral
Bus Clock
Timer n
Figure 40-1. Block diagram of the PIT
NOTE
Refer to the Chip Configuration information for the number of
PIT channels used in this MCU.
40.1.2 Features
The main features of this block are:
• Timers can generate DMA trigger pulses
• Timers can generate interrupts
• All interrupts are maskable
• Independent timeout periods for each timer
40.2 Signal Description
The PIT module has no external pins.
1064
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.