K60P100M100SF2RM Datasheet, PDF (1604/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register definition
52.4.15 Interrupt Signal Enable Register (SDHC_IRQSIGEN)
This register is used to select which interrupt status is indicated to the host system as the
interrupt. These status bits all share the same interrupt line. Setting any of these bits to 1
enables interrupt generation. The corresponding status register bit will generate an
interrupt when the corresponding interrupt signal enable bit is set.
Address: SDHC_IRQSIGEN is 400B_1000h base + 38h offset = 400B_1038h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDHC_IRQSIGEN field descriptions
Field
31–29
Reserved
28
DMAEIEN
27–25
Reserved
24
AC12EIEN
23
Reserved
22
DEBEIEN
21
DCEIEN
Description
This read-only field is reserved and always has the value zero.
DMA Error Interrupt Enable
0b Masked
1b Enabled
This read-only field is reserved and always has the value zero.
Auto CMD12 Error Interrupt Enable
0b Masked
1b Enabled
This read-only field is reserved and always has the value zero.
Data End Bit Error Interrupt Enable
0b Masked
1b Enabled
Data CRC Error Interrupt Enable
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1604
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.