K60P100M100SF2RM Datasheet, PDF (494/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Initialization/application information
3. Enable error interrupts in the EEI register if so desired.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the ERQ register.
6. Request channel service via either:
• Software: setting the TCDn_CSR[START] bit
• Hardware: slave device asserting its eDMA peripheral request signal
After any channel requests service, a channel is selected for execution based on the
arbitration and priority levels written into the programmer's model. The eDMA engine
reads the entire TCD, including the TCD control and status fields, as shown in the
following table, for the selected channel into its internal address path module.
As the TCD is read, the first transfer is initiated on the internal bus unless a configuration
error is detected. Transfers from the source, as defined by the source address,
TCDn_SADDR, to the destination, as defined by the destination address,
TCDn_DADDR, continue until the specified number of bytes (TCDn_NBYTES) are
transferred.
When the transfer is complete, the eDMA engine's local TCDn_SADDR,
TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory and any
minor loop channel linking is performed, if enabled. If the major loop is exhausted,
further post processing executes, such as interrupts, major loop channel linking, and
scatter/gather operations, if enabled.
Table 21-297. TCD Control and Status fields
TCDn_CSR field
name
START
ACTIVE
DONE
D_REQ
BWC
E_SG
INT_HALF
INT_MAJ
Description
Control bit to start channel explicitly when using a software initiated DMA service (Automatically
cleared by hardware)
Status bit indicating the channel is currently in execution
Status bit indicating major loop completion (cleared by software when using a software initiated
DMA service)
Control bit to disable DMA request at end of major loop completion when using a hardware initiated
DMA service
Control bits for throttling bandwidth control of a channel
Control bit to enable scatter-gather feature
Control bit to enable interrupt when major loop is half complete
Control bit to enable interrupt when major loop completes
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
494
Freescale Semiconductor, Inc.