K60P100M100SF2RM Datasheet, PDF (1143/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 44 10/100-Mbps Ethernet MAC (ENET)
44.3.5 Ethernet Control Register (ENET_ECR)
ECR is a read/write user register, though hardware may alter fields in this register as
well. It controls many of the high level features of the Ethernet MAC, including legacy
FEC support through the EN1588 bit.
Address: ENET_ECR is 400C_0000h base + 24h offset = 400C_0024h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
1
0
W
Reset 1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
W
Reset 0
Field
31–28
Reserved
27–8
Reserved
7
STOPEN
6
DBGEN
5
Reserved
4
EN1588
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ENET_ECR field descriptions
Description
This read-only field is reserved and always has the value one.
This read-only field is reserved and always has the value zero.
STOPEN Signal Control
Controls device behavior in doze mode.
In doze mode, if this bit is set then all the clocks of the ENET assembly are disabled (except the RMII/MII
clock). Doze mode is like a conditional stop mode entry for the ENET assembly depending on
ECR[STOPEN].
NOTE: If module clocks are gated in this mode, the module can still wake the system after receiving a
magic packet in stop mode. MAGICEN must be set prior to entering sleep/stop mode.
Debug enable
Enables the MAC to enter hardware freeze mode when the device enters debug mode.
0 MAC continues operation in debug mode.
1 MAC enters hardware freeze mode when the processor is in debug mode.
This read-only field is reserved and always has the value zero.
EN1588 enable
Enables enhanced functionality of the MAC.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1143