K60P100M100SF2RM Datasheet, PDF (476/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
DMA_TCDn_NBYTES_MLOFFYES field descriptions (continued)
Field
9–0
NBYTES
Minor Byte Transfer Count
Description
Number of bytes to be transferred in each service request of the channel.
As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate
reads and writes perform until the minor byte transfer count has transferred. This is an indivisible
operation and cannot be halted. (Although, it may be stalled by using the bandwidth control field, or via
preemption.) After the minor count is exhausted, the SADDR and DADDR values are written back into the
TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major
iteration count is completed, additional processing is performed.
21.3.23 TCD Last Source Address Adjustment (DMA_TCD_SLAST)
Addresses: 4000_8000h base + 100Ch offset + (32d × n), where n = 0d to 15d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SLAST
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
Field
31–0
SLAST
DMA_TCDn_SLAST field descriptions
Last source Address Adjustment
Description
Adjustment value added to the source address at the completion of the major iteration count. This value
can be applied to restore the source address to the initial value, or adjust the address to reference the
next data structure.
21.3.24 TCD Destination Address (DMA_TCD_DADDR)
Addresses: 4000_8000h base + 1010h offset + (32d × n), where n = 0d to 15d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DADDR
W
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
476
Freescale Semiconductor, Inc.