SH7763 Datasheet, PDF (998/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.86 Transmit Descriptor Final Flag Register (TDFFR)
TDFFR indicates whether the transmit descriptor for which the E-DMAC has just completed the
write-back processing and whose start address is stored in TDFXR is at the end of the transmit
descriptor queue (descriptor list).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0














 TDLF
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Bit
31 to 1
Bit Name

Initial
Value
All 0
0
TDLF
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Transmit Descriptor Queue Last Flag
Indicates whether the transmit descriptor for which the
E-DMAC has just completed the write-back processing
and whose start address is stored in TDFXR is at the
end of the transmit descriptor queue (descriptor list).
0: Not the last descriptor in the transmit descriptor
queue
1: Last descriptor in the transmit descriptor queue
Rev. 1.00 Oct. 01, 2007 Page 932 of 1956
REJ09B0256-0100