SH7763 Datasheet, PDF (887/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.9 PHY Status Register (PSR)
PSR is a read-only register that can read interface signals from the PHY-LSI.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0














 LMON
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
31 to 1
Bit Name

Initial
Value
All 0
0
LMON
0
R/W
R
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
ET_LNKSTA Pin Status
The Link status can be read by connecting the Link
signal output from the PHY-LSI to the ET_LNKSTA pin.
For the polarity, refer to the specifications of the PHY-
LSI to be connected.
Rev. 1.00 Oct. 01, 2007 Page 821 of 1956
REJ09B0256-0100