SH7763 Datasheet, PDF (617/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(1) Master Read/Write Cycle Timing
Figures13.17 is an example of a single-write cycle in host bus bridge mode. Figure 13.18 is an
example of a single read cycle in host bus bridge mode. Figure 13.19 is an example of a burst
write cycle in normal mode. And Figure 13.20 is an example of a burst read cycle in normal mode.
Note that the response speed of DEVSEL and TRDY differs according to the connected target
device. In host bus bridge mode, master accesses always use single read/write cycles. The issuing
of configuration transfers is only possible in host bus bridge mode.
PCICLK
AD[31:0]
PAR
CBE[3:0]
(C/BE[3:0])
PCIFRAME
IRDY
DEVSEL
TRDY
LOCK
IDSEL
REQ
GNT
Addr D0
AP DP0
Com BE0
[Legend]
Addr: PCI space address
AP: Address parity
Com: Command
Dn: nth data
DPn: nth data parity
BEn: nth data byte enable
Figure 13.17 Master Write Cycle in Host Bus Bridge Mode (Single)
Rev. 1.00 Oct. 01, 2007 Page 551 of 1956
REJ09B0256-0100