SH7763 Datasheet, PDF (453/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
This LSI
CLKOUT
CSn
BS
RD
RDWR
D31 to D0
RDY
MPX device
CLK
CS
BS
FRAME
WE
I/O31 to I/O0
RDY
Figure 11.21 Example of 32-Bit Data Width MPX Connection
The MPX interface timing is shown below.
When the MPX interface is used for areas 1, 2, and 4 to 6, a bus size of 32 bits should be specified
by CSnBCR.
In wait control, either waits by CSnWCR or waits by the RDY pin can be inserted.
In a read, one wait cycle is automatically inserted after address output, even if CSnWCR is cleared
to 0.
CLKOUT
RD/FRAME
D31 to D0
CSn
RDWR
T_m1
T_md1w
T_md1
A
D0
RDY
BS
DACK
(DA)
DA: Dual address DMA
Figure 11.22 MPX Interface Timing 1 (Single Read Cycle, IW = 0, No External Wait)
Rev. 1.00 Oct. 01, 2007 Page 387 of 1956
REJ09B0256-0100