SH7763 Datasheet, PDF (1336/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 SIM Card Module (SIM)
Table 30.5 Example of Bit Rates (bits/s) for SCBRR Settings
(Pck0 = 66.6 MHz, SCSMPL = 371)
SCBRR Setting
SCK Frequency (MHz)
Bit Rate (bits/s)
7
4.16
11190
6
4.76
12788
5
5.55
14919
4
6.66
17903
Note: The bit rate is a value that is rounded off below the decimal point.
30.4.5 Data Transmit/Receive Operation
(1) Initialization
Prior to data transmission and reception, the following procedure should be used to initialize the
smart card interface. Initialization is also necessary when switching from transmit mode to receive
mode, and when switching from receive mode to transmit mode. An example of the initialization
process is shown in the flowchart of figure 30.4.
Step (1) to step (7) of figure 30.4 correspond to the following operation.
1. Clear the TE and RE bits in the serial control register (SCSCR) to 0.
2. Clear the error flags PER, ORER, ERS, and WAIT_ER in the serial status register (SCSSR) to
0.
3. Set the parity bit (O/E bit) in the serial mode register (SCSMR).
4. Set the LCB, PB, SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR).
5. Set the value corresponding to the bit rate to the bit rate register (SCBRR).
6. Set the clock source select bits (CKE[1] and CKE[0] bits) in the serial control register
(SCSCR). At this time, the TIE, RIE, TE, RE, TEIE, and WAIT_IE bits should be cleared to 0.
If the CKE[0] bit is set to 1, a clock signal is output from the SIM_CLK pin.
7. After waiting at least 1 etu, set the TIE, RIE, TE, RE, TEIE, and WAIT_IE bits in SCSCR.
Except for self-check, the TE bit and RE bit should not be set simultaneously.
Rev. 1.00 Oct. 01, 2007 Page 1270 of 1956
REJ09B0256-0100