SH7763 Datasheet, PDF (1597/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.22 EP4 Data Register (EPDR4)
EPDR4 is a 128-byte receive FIFO buffer for endpoint 4. EPDR4 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. The number of receive byte is displayed in
the EP4 receive data size register. The receive data is fixed when an SOF packet is received.
Accordingly, all receive data must be read until the next SOF packet is received. When the next
SOF packet is received, the FIFO side is automatically switched over, and the previous data will
not be possible to be read. This FIFO buffer can be initialized by means of EP4CLR in the FCLR1
register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————
D[7:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
31 to 8 
7 to 0 D[7:0]
Initial Value R/W Description
Undefined R Reserved
These bits are always read as undefined value.
Undefined R Data register for endpoint 4 transfer
Rev. 1.00 Oct. 01, 2007 Page 1531 of 1956
REJ09B0256-0100