SH7763 Datasheet, PDF (1210/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.10 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit register that indicates the number of transmit data bytes stored in SCFTDR.
SCFDR can always be read from the CPU.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

TDN[4:0]

RDN[4:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
15 to 13 —
Initial
Value
All 0
12 to 8 TDN[4:0] All 0
7 to 5 —
All 0
4 to 0 RDN[4:0] All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R
These bits show the number of untransmitted data
bytes in SCFTDR. A value of H'00 indicates that there
is no transmit data, and a value of H'10 indicates that
SCFTDR is full of transmit data (16-bytes).
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R
These bits show the number of receive data bytes in
SCFRDR. A value of H'00 indicates that there is no
receive data, and a value of H'10 indicates that
SCFRDR is full of receive data (16-bytes).
Rev. 1.00 Oct. 01, 2007 Page 1144 of 1956
REJ09B0256-0100