SH7763 Datasheet, PDF (1183/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
Thus, the reception margin in asynchronous mode is given by formula (1).
1
| D - 0.5 |
M= (0.5 -
) - (L - 0.5) F -
(1 + F) × 100 % .................. (1)
2N
N
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
From equation (1), if F = 0 and D = 0.5, the reception margin is 46.875%, as given by formula (2).
When D = 0.5 and F = 0:
M = (0.5 – 1 / (2 × 16) ) × 100% = 46.875% ............................................... (2)
However, this is a theoretical value. A reasonable margin to allow in system designs is 20% to
30%.
(6) When Using the DMAC
When using an external clock as the synchronization clock, after SCFTDR is updated by the
DMAC, an external clock should be input after at least five peripheral clock (Pck) cycles. A
malfunction may occur when the transfer clock is input within four cycles after updating SCFTDR
(see figure 27.23).
SCIF_CLK
t
TDRE
SCIF_TXD
D0
D1
D2
D3
D4
D5
D6
D7
Note: When the SCIF is operated on an external clock, set t > 4.
Figure 27.23 Example of Synchronization Clock Transfer by DMAC
Rev. 1.00 Oct. 01, 2007 Page 1117 of 1956
REJ09B0256-0100