SH7763 Datasheet, PDF (1207/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3.8 Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that set the serial transmission/reception bit rate in accordance with the
baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR.
SCBRR can always be read from and written to by the CPU.
This baud rate generator is intended for Pck0, Pck0/4, Pck0/16, and Pck0/64. For details on the
baud rate generator for external clock, see section 28.6, Baud Rate Generator for External Clock
(BRG).
The SCBRR setting is found from the following equation.
Asynchronous mode:
N=
Pck0
64 × 2^{2n - 1} × B
× 10⁶ - 1
Clocked synchronous mode:
N=
Pck0
8 × 2^{2n - 1} × B
× 10⁶ - 1
Where B: Bit rate (bits/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
Pck0: Peripheral module operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See Table 28.4 for the relation between n and the clock.)
Table 28.4 SCSMR Settings
n
Clock
CKS1
0
Pck0
0
1
Pck0/4
0
2
Pck0/16
1
3
Pck0/64
1
SCSMR Setting
CKS0
0
1
0
1
Rev. 1.00 Oct. 01, 2007 Page 1141 of 1956
REJ09B0256-0100