SH7763 Datasheet, PDF (147/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 4 Pipelining
(1-1) BF, BF/S, BT, BT/S, BRA, BSR:1 issue cycle + 0 to 2 branch cycles
I1
I2
ID E1/S1 E2/s2 E3/s3 WB
Note: In branch instructions that are categorized
as (1-1), the number of branch cycles may
be reduced by prefetching.
(I1) (I2) (ID) (Branch destination instruction)
(1-2) JSR, JMP, BRAF, BSRF: 1 issue cycle + 3 branch cycles
I1
I2
ID E1/S1 E2/S2 E3/S3 WB
(I1) (I2) (ID) (Branch destination instruction)
(1-3) RTS: 1 issue cycle + 0 to 3 branch cycles
I1
I2
ID E1/S1 E2/S2 E3/S3 WB
Note: The number of branch cycles may be
0 by prefetching instruction.
(I1) (I2) (ID) (Branch destination instruction)
(1-4) RTE: 4 issue cycles + 1 branch cycles
I1
I2
ID s1
s2
s3 WB
ID E1s1 E2s2 E3s3 WB
ID
ID
(I1) (I2) (ID) _{(Branch destination instruction)}
(1-5) TRAPA: 8 issue cycles + 5 cycles + 1 branch cycle
I1 I2 ID S1 S2 S3 WB
ID E1s1 E2s2 E3s3 WB
Note: It is 14 cycles to the ID stage in the first
instruction of exception handler.
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 _{E3s3 WB}
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 E3s3 WB
(I1) (I2) (ID)
(1-6) SLEEP: 2 issue cycles
I1
I2
ID
S1
S2
S3 WB
ID E1s1 E2s2 E3s3 WB
Note: It is not constant cycles to
the clock halted period.
Figure 4.2 Instruction Execution Patterns (1)
Rev. 1.00 Oct. 01, 2007 Page 81 of 1956
REJ09B0256-0100