SH7763 Datasheet, PDF (370/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Interrupt Source
INTEVT Interrupt MASK/CLEAR
Code Priority Register
Interrupt
Source
Register
Detail
Source
Register
Priority
in the
Source
SSI2
SSII2
H'EC0 INT2PRI8 INT2MSKR1[2]
[20:16] _{INT2MSKCR1[2]}
INT2A01[2] —
INT2A11[2]
SSI3
SSII3
H'EE0 INT2PRI8 INT2MSKR1[3]
[28:24] _{INT2MSKCR1[3]}
INT2A01[3] —
INT2A11[3]
SCIF2
ERI2
RXI2
BRI2
TXI2
H'F00
H'F20
H'F40
H'F60
INT2PRI7 INT2MSKR1[25]
[28:24] _{INT2MSKCR1[25]}
INT2A01 INT2B6[0]
[25]
INT2B6[1]
INT2A11
[25]
INT2B6[2]
INT2B6[3]
High
Low
GPIO
CH0
CH1
H'F80
H'FA0
INT2PRI7 INT2MSKR[25]
[20:16] _{INT2MSKCR[25]}
INT2A0[25] INT2B7
INT2A1[25] ^[3:0]
INT2B7
[11:8]
High
CH2
H'FC0
INT2B7
[19:16]
CH3
H'FE0
INT2B7
[27:24] Low
Notes: 1. ITI: Interval timer interrupt
TUNI0 to TUNI5: TMU channel 0 to 5 under flow interrupt
TICPI2: TMU channel 2 input capture interrupt
DMINT0 to DMINT5: DMAC channel 0 to 5 transfer end interrupt
DMAE: DMAC address error interrupt (channel 0 to 5)
ERI0, ERI1: SCIF channel 0, 1 receive error interrupt
RXI0, RXI1: SCIF channel 0, 1 receive data full interrupt
BRI0, BRI1: SCIF channel 0, 1 break interrupt
TXI0, TXI1: SCIF channel 0, 1 transmission data empty interrupt
2. This bit is reserved in the R5S77631.
Default
Priority
High
Low
Rev. 1.00 Oct. 01, 2007 Page 304 of 1956
REJ09B0256-0100