SH7763 Datasheet, PDF (873/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.1 Software Reset Register (ARSTR)
ARSTR resets all blocks (E-MAC, TSU, and E-DMAC) in the GETHER. By writing 1 to the
ARST bit in this register, a software reset is issued to all blocks of the GETHER (for 256 cycles of
external bus clock Bck). The ARST bit is always read as 0. While a software reset is issued,
register access to all blocks of the GETHER is prohibited.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0














 ARST
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Initial
Bit
Bit Name Value R/W Description
31 to 1 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
ARST
0
R/W Software Reset
When 1 is written to this bit, a software reset is issued
to all blocks of the GETHER (for 256 cycles of external
bus clock Bck). Writing 0 does not affect this bit. This
bit is always read as 0. While a software reset is
issued, register access to all blocks of the GETHER is
prohibited. The following registers are not initialized by
a software reset.
TSU_ADRH0 to TSU_ADRH31, TSU_ADRL0 to
TSU_ADRL31, TXNLCR0, TXNLCR1, TXALCR0,
TXALCR1, RXNLCR0, RXNLCR1, RXALCR0,
RXALCR1, FWNLCR0, FWNLCR1, FWALCR0,
FWALCR1
When relay operations from the E-MAC-1 to E-MAC-0
or from the E-MAC-0 to E-MAC-1 are enabled, a reset
must be issued using this bit. A software reset issued
by the SWRT and SWRR bits in EDMR does not reset
the transfer switching unit (TSU) performing data
transfer between the E-MAC-1 and E-MAC-0.
Rev. 1.00 Oct. 01, 2007 Page 807 of 1956
REJ09B0256-0100