SH7763 Datasheet, PDF (597/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
For PCI memory space 0 accesses, bits 23 to 18 of a SuperHyway bus address are controlled by
PCI memory bank mask register 0 (PCIMBMR0).
Note: In the following items and figures, “SH” means the SuperHyway bus of this LSI and
“PCI” means the PCI local bus.
• PCIMBMR0 [23:18] B'1111 11: PCI address [23:18] = SH address [23:18]
• PCIMBMR0 [23:18] B'0111 11: PCI address [23:18] = PCIMBR0 [23], SH address [22:18]
• PCIMBMR0 [23:18] B'0000 01: PCI address [23:18] = PCIMBR0 [23:19], SH address [18]
• PCIMBMR0 [23:18] B'0000 00: PCI address [23:18] = PCIMBR0 [23:18]
The upper eight bits ([31:24]) of a SuperHyway bus address are replaced with bits 31 to 24 in PCI
memory bank register 0 (PCIMBR0).
SH address
31 24 23
18 17
0
31 24 23
18 17
0
PCI address
PCIMBMR0
31 24 23
18 17
MSBAM0
mask
0
31 24 23
18 17
0
PCIMBR0
PMSBA0
Figure 13.3 SuperHyway Bus to PCI Local Bus Address Translation
(PCI Memory Space 0)
For PCI memory space 1 accesses, bits 25 to 18 of a SuperHyway address are controlled by PCI
memory bank mask register 1 (PCIMBMR1).
• PCIMBMR1 [25:18] B'11 1111 11: PCI address [25:18] = SH address [25:18]
• PCIMBMR1 [25:18] B'01 1111 11: PCI address [25:18] = PCIMBR1 [25], SH address [24:18]
• PCIMBMR1 [25:18] B'00 0000 01: PCI address [25:18] = PCIMBR1 [25:19], SH address [18]
• PCIMBMR1 [25:18] B'00 0000 00: PCI address [25:18] = PCIMBR1 [25:18]
The upper six bits ([31:26]) of a SuperHyway bus address are replaced with bits 31 to 26 in PCI
memory bank register 1 (PCIMBR1).
Rev. 1.00 Oct. 01, 2007 Page 531 of 1956
REJ09B0256-0100