SH7763 Datasheet, PDF (1236/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(5) Serial Data Reception (Clocked Synchronous Mode)
Figures 28.16 and 28.17 show a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
When switching the operating mode from asynchronous mode to clocked synchronous mode
without initializing the SCIF, make sure that the ORER flag is cleared to 0.
Initialization
[1]
Start of reception
[1] SCIF initialization:
See Sample SCIF Initialization Flowchart in figure
28.13.
Read ORER flag in SCLSR
ORER = 1?
Yes
[2]
[2] Receive error handling:
Read the ORER flag in SCLSR to identify any error,
perform the appropriate error handling, then clear
the ORER flag to 0.
Transmission/reception cannot be resumed while the
ORER flag is set to 1.
No
Error handling _{[3] SCIF status check and receive data read:}
Read SCFSR and check that RDF = 1, then read the
Read RDF flag in SCFSR
[3]
receive data in SCFRDR, and clear the RDF flag to
0. The transition of the RDF flag from 0 to 1 can also
No
RDF = 1?
be identified by an RXI interrupt.
Yes
Read receive data in
SCFRDR, and clear RDF
[4]
flag in SCFSR to 0
No
All data received?
Yes
Clear RE bit in SCSCR to 0
[4] Serial reception continuation procedure:
To continue serial reception, read at least the receive
trigger set number of receive data bytes from SCFRDR,
read 1 from the RDF flag, then clear the RDF flag to 0.
The number of receive data bytes in SCFRDR can
be ascertained by reading SCFDR.
However, as starting up the DMAC using RXI and
reading the value of SCFDR automatically clears bit
RDF, clearing bit RDF is not required.
End of reception
Figure 28.16 Sample Serial Reception Flowchart (1)
Rev. 1.00 Oct. 01, 2007 Page 1170 of 1956
REJ09B0256-0100