SH7763 Datasheet, PDF (409/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Initial
Bit
Bit Name Value R/W Description
15

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14 to 12 IWRRS
111
R/W Idle Cycles between Read-Read to Same Space
Specify the number of idle cycles to be inserted after an
access to a memory connected to the space is
completed. The target cycles are read-read cycles to
the same space. For details, see section 11.5.8, Wait
Cycles between Accesses.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 3 idle cycles inserted
100: 4 idle cycles inserted
101: 5 idle cycles inserted
110: 6 idle cycles inserted
111: 7 idle cycles inserted
11, 10 BST
01
R/W Burst Length
When a burst ROM interface is used, these bits specify
the number of accesses in a burst. The MPX interface
is not affected.
00: 4 consecutive accesses (Can be used with 8-, 16-,
or 32-bit bus width)
01: 8 consecutive accesses (Can be used with 8-, 16-,
or 32-bit bus width)
10: 16 consecutive accesses (Can be used with 8-, or
16-bit bus width)
11: 32 consecutive accesses (Can be used with 8-bit
bus width)
Rev. 1.00 Oct. 01, 2007 Page 343 of 1956
REJ09B0256-0100