SH7763 Datasheet, PDF (523/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
Name
SH*¹ PCI*¹
Abbreviation R/W R/W P4 address
Access
Area 7 address Size*²
PCI memory bank register 0
PCIMBR0
R/W — H'FE04 01E0 H'1E04 01E0 32
PCI memory bank mask register 0 PCIMBMR0 R/W — H'FE04 01E4 H'1E04 01E4 32
PCI memory bank register 1
PCIMBR1
R/W — H'FE04 01E8 H'1E04 01E8 32
PCI memory bank mask register 1 PCIMBMR1 R/W — H'FE04 01EC H'1E04 01EC 32
PCI memory bank register 2
PCIMBR2
R/W — H'FE04 01F0 H'1E04 01F0 32
PCI memory bank mask register 2 PCIMBMR2 R/W — H'FE04 01F4 H'1E04 01F4 32
PCI I/O bank register
PCIIOBR
R/W — H'FE04 01F8 H'1E04 01F8 32
PCI I/O bank master register
PCIIOBMR R/W — H'FE04 01FC H'1E04 01FC 32
PCI cache snoop control register 0 PCICSCR0 R/W — H'FE04 0210 H'1E04 0210 32
PCI cache snoop control register 1 PCICSCR1 R/W — H'FE04 0214 H'1E04 0214 32
PCI cache snoop address register 0 PCICSAR0 R/W — H'FE04 0218 H'1E04 0218 32
PCI cache snoop address register 1 PCICSAR1 R/W — H'FE04 021C H'1E04 021C 32
PCI PIO*³ data register
PCIPDR
R/W — H'FE04 0220 H'1E04 0220 32
Notes: 1. SH: SuperHyway bus (internal bus). PCI: PCI local bus. WC: Cleared by writing 1
(Writing of 0 is no effect). —: Accessing is prohibited.
2. When accessing a register, do not use a size smaller than the register's access size.
3. PIO: Programmed I/O.
Rev. 1.00 Oct. 01, 2007 Page 457 of 1956
REJ09B0256-0100