SH7763 Datasheet, PDF (1293/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
Figure 29.8 shows an example of the control data interface timing by the secondary FS.
1/2 frame
1 frame
1/2 frame
SIOF_SCK
SIOF_SYNC
SIOF_TXD
SIOF_RXD
Normal FS
Secondary FS
Normal FS
L-channel
data
Slot
No.0
Control
channel 0
Slot
LSB=1 (Secondary FS request) _No.0
Specifications:TRMD[1:0] = 01, REDG = 0,
TDLE = 1,
TDLA[3:0] = 0000,
RDLE = 1,
RDLA[3:0] = 0000,
CD0E = 1,
CD0A[3:0] = 0000,
FL[3:0] = 1110 (Frame length: 128 bits),
TDRE = 0,
TDRA[3:0] = 0000,
RDRE = 0,
RDRA[3:0] = 0000,
CD1E = 0,
CD1A[3:0] = 0000
Figure 29.8 Control Data Interface (Secondary FS)
29.4.6 FIFO
(1) Overview
The transmit and receive FIFOs of the SIOF have the following features.
• 16-stage 32-bit FIFOs for transmission and reception
• The FIFO pointer can be updated in one read or write cycle regardless of access size of the
CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.)
(2) Transfer Request
The transfer request of the FIFO can be issued to the CPU or DMAC as the following interrupt
sources.
• FIFO transmit request: TDREQ (transmit interrupt source)
• FIFO receive request: RDREQ (receive interrupt source)
The request conditions for FIFO transmit or receive can be specified individually. The request
conditions for the FIFO transmit and receive are specified by the bits TFWM[2:0] and the bits
RFWM[2:0] in SIFCTR, respectively. Table 29.11 and table 29.12 summarize the conditions
specified by SIFCTR.
Rev. 1.00 Oct. 01, 2007 Page 1227 of 1956
REJ09B0256-0100