SH7763 Datasheet, PDF (394/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
11.3.2 Memory Bus Width
The memory bus width of the LBSC can be set independently for each area. For area 0, a bus
width of 8, 16, or 32 bits is set according to the external pin settings at a power-on reset by the
PRESET pin. The correspondence between the external pins (MD4 and MD3) and the bus width at
a power-on reset is shown in table 11.3.
Table 11.3 Setting of bus width for area 0
MD4
0
0
1
1
MD3
0
1
0
1
Bus Width
32 bits (MPX interface)
8 bits
16 bits
32 bits
When either the SRAM or ROM interface is used in areas 1 to 2 and 4 to 6, a bus width of 8, 16,
or 32 bits can be selected through the CSn bus control register (CSnBCR). When the burst ROM
interface is used, a bus width of 8, 16, or 32 bits can be selected. When the byte-control SRAM
interface is used, a bus width of 16 or 32 bits can be selected. When the MPX interface is used, a
bus width of 32 bits should be selected.
When using the PCMCIA interface, a bus width of 8 or 16 bits should be selected. For details, see
section 11.5.5, PCMCIA Interface.
For details, see section 11.4.3, CSn Bus Control Register (CSnBCR).
The bus width of the DDR-SDRAM and the PCI interfaces is 32 bits. For details, see section 12,
DDR-SDRAM Interface (DDRIF), and section 13, PCI Controller (PCIC).
The addresses of area 7 (H'1C00 0000 to H'1FFF FFFF) are reserved and must not be used.
Rev. 1.00 Oct. 01, 2007 Page 328 of 1956
REJ09B0256-0100