SH7763 Datasheet, PDF (1602/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.27 Trigger Register (TRG)
TRG generates one-shot triggers FIFO for each endpoint of EP0s, EP0i, EP0o, EP1, EP2, and
EP3. The packet enable trigger for the IN FIFO register and read complete trigger for the OUT
FIFO register are triggers to be given.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
EP3 EP1 EP2
PKTE RDFN PKTE
—
EP0s EP0o EP0i
RDFN RDFN PKTE
Initial value: — — — — — — — — 0
0
0
0
0
0
0
0
R/W: R R R R R R R R W W W W W W W W
Bit Bit Name
31 to 8 
7

6
EP3 PKTE
5
EP1 RDFN
4
EP2 PKTE
3

2
EP0s RDFN
1
EP0o RDFN
0
EP0i PKTE
Initial Value R/W Description
Undefined R Reserved
These bits are always read as undefined value.
Write value should always be 0.
0
W Reserved
The write value should always be 0.
0
W EP3 Packet Enable
0
W EP1 Read Complete
0
W EP2 Packet Enable
0
W Reserved
The write value should always be 0.
0
W EP0s Read Complete
0
W EP0o Read Complete
0
W EP0i Packet Enable
Rev. 1.00 Oct. 01, 2007 Page 1536 of 1956
REJ09B0256-0100