SH7763 Datasheet, PDF (25/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

26.4.7 10-Bit Address Format........................................................................................ 1048
26.4.8 Master Transmit Operation ................................................................................. 1050
26.4.9 Master Receive Operation................................................................................... 1052
26.5 Programming Examples................................................................................................... 1054
26.5.1 Master Transmitter.............................................................................................. 1054
26.5.2 Master Receiver .................................................................................................. 1055
26.5.3 Master Transmitter—Restart—Master Receiver ................................................ 1056
Section 27 Serial Communication Interface with FIFO (SCIF) ......................1059
27.1 Features............................................................................................................................ 1059
27.2 Input/Output Pins ............................................................................................................. 1065
27.3 Register Descriptions ....................................................................................................... 1066
27.3.1 Receive Shift Register (SCRSR)......................................................................... 1068
27.3.2 Receive FIFO Data Register (SCFRDR) ............................................................ 1068
27.3.3 Transmit Shift Register (SCTSR) ....................................................................... 1069
27.3.4 Transmit FIFO Data Register (SCFTDR) ........................................................... 1069
27.3.5 Serial Mode Register (SCSMR).......................................................................... 1070
27.3.6 Serial Control Register (SCSCR)........................................................................ 1073
27.3.7 Serial Status Register (SCFSR) .......................................................................... 1077
27.3.8 Bit Rate Register (SCBRR) ................................................................................ 1083
27.3.9 FIFO Control Register (SCFCR) ........................................................................ 1084
27.3.10 Transmit FIFO Data Count Register (SCTFDR) ................................................ 1086
27.3.11 Receive FIFO Data Count Register (SCRFDR).................................................. 1086
27.3.12 Serial Port Register (SCSPTR) ........................................................................... 1087
27.3.13 Line Status Register (SCLSR) ............................................................................ 1090
27.3.14 Serial Error Register (SCRER) ........................................................................... 1091
27.4 Operation ......................................................................................................................... 1092
27.4.1 Overview............................................................................................................. 1092
27.4.2 Operation in Asynchronous Mode ...................................................................... 1094
27.4.3 Operation in Clocked Synchronous Mode .......................................................... 1104
27.5 SCIF Interrupt Sources and the DMAC ........................................................................... 1113
27.6 Usage Notes ..................................................................................................................... 1115
Section 28 Serial Communication Interface with FIFO/IrDA Interface
(SCIF/IrDA) ...................................................................................1119
28.1 Features............................................................................................................................ 1119
28.2 Input/Output Pins ............................................................................................................. 1123
28.3 Register Descriptions ....................................................................................................... 1124
28.3.1 Receive Shift Register (SCRSR)......................................................................... 1126
28.3.2 Receive FIFO Data Register (SCFRDR) ............................................................ 1126
Rev. 1.00 Oct. 01, 2007 Page xxv of lxvi