SH7763 Datasheet, PDF (1502/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
Note: 1. These bits are readable/writable bits. If writing 0, these bits are initialized, although
writing 1 is ignored.
2. At manual reset, the bit is undefined.
34.3.3 Transmit Data Register (SSITDR)
SSITDR is a 32-bit register that stores data to be transmitted.
Data written to SSITDR is transferred to the shift register as it is required for transmission. If the
data word length is less than 32 bits then its alignment should be as defined by the PDTA control
bit.
Reading this register will return the data in the buffer.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0
0
0
00
0
0
0
00
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0 0
0
0
00
0
0
0
00
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
34.3.4 Receive Data Register (SSIRDR)
SSIRDR is a 32-bit register that stores the received data.
Data in SSIRDR is transferred from the shift register as each data word is received. If the data
word length is less than 32 bits then its alignment should be as defined by the PDTA control bit in
SSICR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0
0
0
00
0
0
0
00
0
0
0
0
0
R/W: R
R
R
R
R
R
R
RR
R
R
R
R
RR
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0 0
0
0
00
0
0
0
00
0
0
0
0
0
R/W: R
R
R
R
R
R
R
RR
R
R
R
R
RR
R
Rev. 1.00 Oct. 01, 2007 Page 1436 of 1956
REJ09B0256-0100