SH7763 Datasheet, PDF (1598/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.23 EP5 Data Register (EPDR5)
EPDR5 is a 128-byte transmit FIFO buffer for endpoint 5. EPDR5 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO
buffer and an SOF packet is received, one packet of transmit data is fixed, and the dual-FIFO
buffer is switched over. This FIFO buffer can be initialized by means of EP5CLR and EP5CCLR
in the FCLR1 register. (EP5CLR initializes both FIFOs and EP5CCLR initializes one FIFO which
is connected to the CPU.)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————
D[7:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R W W W W W W W W
Bit
Bit Name
31 to 8 
7 to 0 D[7:0]
Initial Value R/W Description
Undefined R Reserved
These bits are always read as undefined value.
Write value should always be 0.
Undefined W Data register for endpoint 5 transfer
Rev. 1.00 Oct. 01, 2007 Page 1532 of 1956
REJ09B0256-0100