SH7763 Datasheet, PDF (937/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.48 CAM Entry Table Busy Register (TSU_ADSBSY)
When CAM entry table registers (TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to
TSU_ADRL31) are set by register writing, the ADSBSY bit in this register is set to 1 (when the
process of reflecting the contents of the CAM entry table registers in the CAM controller is
completed inside the TSU, the ADSBSY bit is automatically restored to 0).
Access to TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to TSU_ADRL31 is prohibited,
while the ADSBSY bit in this register is set to 1. This register is a read-only status register, which
must not be written to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0















ADS
BSY
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
31 to 1
Bit Name

0
ADSBSY
Initial
Value
All 0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R CAM Entry Table Setting Busy
When TSU_ADRH0 to TSU_ADRH31 and
TSU_ADRL0 to TSU_ADRL31 are set by register
writing, this bit is set to 1. When the process of
reflecting the contents of the CAM entry table registers
in the CAM controller is completed inside the TSU, this
bit is automatically restored to 0. Access to
TSU_ADRH0 to TSU_ADRH31 and TSU_ADRL0 to
TSU_ADRL31 is prohibited, while this bit is set to 1.
Writing to this register is also prohibited.
Rev. 1.00 Oct. 01, 2007 Page 871 of 1956
REJ09B0256-0100