SH7763 Datasheet, PDF (472/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
CLKOUT
BREQ
BACK
A25 to A0
CSn
RDWR
RD
WEn
D31 to D0
(Write)
BS
Asserted for
least 2 cycles
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
Negated
within 2 cycles
Master access
Slave access
Master access
(a) Master mode device access
CLKOUT
BREQ
BACK
A25 to A0
CSn
RDWR
RD
WEn
D31 to D0
(Write)
BS
Must be asserted for
at least 2 cycles
Must be negated
within 2 cycles
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
Master access
Slave access
(b) Slave mode device access
Figure 11.39 Arbitration Sequence
Master access
Rev. 1.00 Oct. 01, 2007 Page 406 of 1956
REJ09B0256-0100