SH7763 Datasheet, PDF (1344/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 SIM Card Module (SIM)
30.5 Usage Notes
The following matters should be noted when using the smart card interface.
(1) Receive Data Timing and Receive Margin
When SCSMPL holds its initial value, the smart card interface operates at a basic clock frequency
372 times the transfer rate.
During reception, the smart card interface samples the falling edge of the start bit using the serial
clock for internal synchronization. Receive data is captured internally at the rising edge of the
186th serial clock pulse. This is shown in figure 30.7.
372 clock pulses
Basic clock
186 clock pulses
0
185
371 0
185
371 0
Received data
(RXD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 30.7 Receive Data Sampling Timing in Smart Card Mode
Hence the receive margin can be expressed as follows.
Formula for receive margin in smart card mode:
1
ʛD ʵ 0.5ʛ
Mʹ ʢ0.5 ʵ ɹ_2Nɹʣʵʢ Lʵ0.5 ʣFʵɹɹɹ_N
ʢLʴFʣʷ100ˋɹ
where
M: Receive margin (%)
N: Ratio of the bit rate to the clock (N = 372)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
Rev. 1.00 Oct. 01, 2007 Page 1278 of 1956
REJ09B0256-0100