SH7763 Datasheet, PDF (125/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 3 Instruction Set
3.2 Addressing Modes
Addressing modes and effective address calculation methods are shown in table 3.2. When a
location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is
translated into a physical memory address. If multiple virtual memory space systems are selected
(SV in MMUCR = 0), the least significant bit of PTEH is also referenced as the access ASID. For
details, see section 6, Memory Management Unit (MMU).
Table 3.2 Addressing Modes and Effective Addresses
Addressing Instruction
Mode
Format
Register
Rn
direct
Register
indirect
@Rn
Effective Address Calculation Method
Effective address is register Rn.
(Operand is register Rn contents.)
Effective address is register Rn contents.
Rn
Rn
Register
indirect
with post-
increment
@Rn+
Effective address is register Rn contents.
A constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand, 8 for a
quadword operand.
Rn
Rn
Rn + 1/2/4/8 ₊
1/2/4/8
Calculation
Formula
—
Rn → EA
(EA: effective
address)
Rn → EA
After instruction
execution
Byte:
Rn + 1 → Rn
Word:
Rn + 2 → Rn
Longword:
Rn + 4 → Rn
Quadword:
Rn + 8 → Rn
Rev. 1.00 Oct. 01, 2007 Page 59 of 1956
REJ09B0256-0100