SH7763 Datasheet, PDF (1835/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 41 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
0
CE
0
R/W Channel Enable
Validates/invalidates the channel. If this bit is 0, all the
other bits in this register are invalid.
0: Invalidates the channel.
1: Validates the channel.
Notes: 1. If the data value is included in the match conditions, be sure to specify the operand
size.
2. If the quadword access is specified and the data value is included in the match
conditions, the upper and lower 32 bits of 64-bit data are each compared with the
contents of both the match data setting register and the match data mask setting
register.
3. The OCBI instruction is handled as longword write access without the data value, and
the PREF, OCBP, and OCBWB instructions are handled as longword read access
without the data value. Therefore, do not include the data value in the match conditions
for these instructions.
Rev. 1.00 Oct. 01, 2007 Page 1769 of 1956
REJ09B0256-0100