SH7763 Datasheet, PDF (1198/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Initial
Bit
Bit Name Value R/W Description
6
RIE
0
R/W Receive Interrupt Enable
Enables or disables generation of a receive-data-full
interrupt (RXI) request when the RDF flag or DR flag in
SCFSR is set to 1, a receive-error interrupt (ERI)
request when the ER flag in SCFSR is set to 1, and a
break interrupt (BRI) request when the BRK flag in
SCFSR or the ORER flag in SCLSR is set to 1.
0: Receive-data-full interrupt (RXI) request, receive-
error interrupt (ERI) request, and break interrupt
(BRI) request disabled
1: Receive-data-full interrupt (RXI) request, receive-
error interrupt (ERI) request, and break interrupt
(BRI) request enabled
Note: An RXI interrupt request can be cleared by
reading 1 from the RDF or DR flag, then clearing
the flag to 0, or by clearing the RIE bit to 0. ERI
and BRI interrupt requests can be cleared by
reading 1 from the ER, BRK, or ORER flag, then
clearing the flag to 0, or by clearing the RIE and
REIE bits to 0.
5
TE
0
R/W Transmit Enable
Enables or disables the start of serial transmission by
the SCIF.
Serial transmission is started when transmit data is
written to SCFTDR while the TE bit is set to 1.
0: Transmission disabled
1: Transmission enabled*
Note: SCSMR and SCFCR settings must be made, the
transmission format decided, and the transmit
FIFO reset, before the TE bit is set to 1.
Rev. 1.00 Oct. 01, 2007 Page 1132 of 1956
REJ09B0256-0100