SH7763 Datasheet, PDF (565/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
Initial
Bit
Bit Name Value R/W
Description
6
SEDIM 0
SH: R/W SERR Detection Interrupt Mask
PCI: R
0: PCIIR.SEDI disabled (masked)
1: PCIIR.SEDI enabled (not masked)
5
DPEITWM 0
SH: R/W Data Parity Error Interrupt Mask for Target Write
PCI: R
0: PCIIR.DPEITW disabled (masked)
1: PCIIR.DPEITW enabled (not masked)
4
PEDITRM 0
SH: R/W PERR Detection Interrupt Mask for Target Read
PCI: R
0: PCIIR.PEDITR disabled (masked)
1: PCIIR.PEDITR enabled (not masked)
3
TADIMM 0
SH: R/W Target-Abort Interrupt Mask for Master
PCI: R
0: PCIIR.TADIM disabled (masked)
1: PCIIR.TADIM enabled (not masked)
2
MADIMM 0
SH: R/W Master-Abort Interrupt Mask for Master
PCI: R
0: PCIIR.MADIM disabled (masked)
1: PCIIR.MADIM enabled (not masked)
1
MWPDIM 0
SH: R/W Master Write Data Parity Error Interrupt Mask
PCI: R
0: PCIIR.MWPDI disabled (masked)
1: PCIIR.MWPDI enabled (not masked)
0
MRDPEIM 0
SH: R/W Master Read Data Parity Error Interrupt Mask
PCI: R
0: PCIIR.MRDPEI disabled (masked)
1: PCIIR.MRDPEI enabled (not masked)
Rev. 1.00 Oct. 01, 2007 Page 499 of 1956
REJ09B0256-0100