SH7763 Datasheet, PDF (530/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(4) PCI Status Register (PCISTATUS)
This status register is used to record status information for PCI bus related events. The definition
of each of the bits is given in the table below. A device may not need to implement all the bits,
depending on device functionality. For instance, since a device that acts as a target does not
inform a target abort, bit 11 does not need to be implemented. Reserved bits should be read-only
and return zero when the bits are read.
Reads from this register operates normally. Writes are slightly different in that bits can be cleared,
but not set. A one bit is cleared whenever the register is written to, and the write data in the
corresponding bit location is a 1. For instance, to clear bit 14 and not affect any other bits, write
the value of B'0100 0000 0000 0000 to the register.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DPE SSE RMA RTA STA
DEVSEL MDPE FBBC  66C CL




Initial value: 0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
SH R/W: R/WC R/WC R/WC R/WC R/WC R R R/WC R R/W R/W R R R R R
PCI R/W: R/WC R/WC R/WC R/WC R/WC R R R/WC R R R R R R R R
Initial
Bit
Bit Name Value R/W
Description
15
DPE
0
SH: R/WC Parity Error Detect Status
PCI: R/WC Indicates that a parity error has been detected in read
data when the PCIC is a master or in write data when
the PCIC is a target.
This bit must be set by the device whenever it detects
a parity error, even if parity error handling is disabled.
0: Device is not detecting parity error.
1: Device is detecting parity error.
14
SSE
0
SH: R/WC System Error Output Status
PCI: R/WC Indicates that the PCIC has asserted the SERR
signal.
0: SERR has not been asserted
1: SERR has been asserted (the value retained until
cleared)
Rev. 1.00 Oct. 01, 2007 Page 464 of 1956
REJ09B0256-0100