SH7763 Datasheet, PDF (956/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.55 CAM Entry Table 0L to 31L Registers (TSU_ADRL0 to TSU_ADRL31)
TSU_ADRL0 to TSU_ADRL31 are entry tables referred to by the CAM in reception and relay.
Each of these registers sets the lower 16 bits of the 48-bit MAC address. Maximum 32 entries of
MAC addresses can be registered.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ADRLn[15:0] (n = 0 to 31)
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
31 to 16 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
15 to 0 ADRLn[15:0] All 0
(n: 0 to 31)
R/W MAC Address Bits
These bits set the lower 16 bits of the MAC address.
When the MAC address is 01-23-45-67-89-AB
(displayed in hexadecimal), set H'000089AB in this
register.
Note:
Set the CAM entry tables following the procedure below.
1. Check that the ADSBSY bit in TSU_ADSBSY is cleared to 0.
2. Set the upper 32 bits of the MAC addresses by TSU_ADRH0 to TSU_ADRH31.
3. Set the lower 16 bits of the MAC addresses by TSU_ADRL0 to TSU_ADRL31.
Rev. 1.00 Oct. 01, 2007 Page 890 of 1956
REJ09B0256-0100