SH7763 Datasheet, PDF (1515/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
(1) Configuration Mode
This mode is entered after the module is released from reset. All required settings in the control
register should be defined in this mode, before the SSI module is enabled by setting the EN bit.
Setting the EN bit causes the SSI module to enter the module enabled mode.
(2) Module Enabled Mode
Operation of the module in this mode depends on the selected operating mode. For details, see
section 34.4.4, Transmit Operation and section 34.4.5, Receive Operation.
34.4.4 Transmit Operation
Transmission can be controlled in one of two ways: either DMA or an interrupt driven.
DMA driven is preferred to reduce the CPU load. In DMA control mode, an underflow or
overflow of data or DMAC transfer end is notified by using an interrupt.
The alternative is using the interrupts that the SSI module generates to supply data as required.
This mode has a higher interrupt load as the SSI module is only double buffered and will require
data to be written at least every system word period.
When disabling the SSI module, the SSI clock* must be supplied continuously until the module
enters in the idle state, indicated by the IIRQ bit.
Figure 34.19 shows the transmit operation in the DMA controller mode. Figure 34.20 shows the
transmit operation in the Interrupt controller mode.
Note: * SCKD = 0: Clock input through the SSI_SCK pin
SCKD = 1: Clock input through the SSI_CLK pin
Rev. 1.00 Oct. 01, 2007 Page 1449 of 1956
REJ09B0256-0100