SH7763 Datasheet, PDF (493/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
Initial
Bit
Bit Name Value R/W
63 to 12 
All 0 R
11 to 8 SPLIT
0001 R/W
7 to 0 
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DDR-SDRAM Memory Configuration
These bits specify the DDR-SDRAM row/column
configuration.
0001: 12 × 9 (= 8 M × 16 bits product)
0011: 13 × 9 (= 16 M × 16 bits product)
0100: 13 × 10 (= 32 M × 16 bits product)
0110: 14 × 10 (= 64 M × 16 bits product)
Other than above: Setting prohibited
The relationship between the SPLIT bits and
row/column is shown in section 12.5.12, Address
Multiplexing.
Reserved
These bits are always read as 0. The write value should
always be 0.
12.4.5 DDR-SDRAM Mode Register (SDMR)
SDMR is used to set the DDR-SDRAM mode register and extended mode register. Since SDMR
is not physically contained in the DDRIF, reading this register is invalid. Only write addresses
have a meaning for the DDR-SDRAM and the write data is ignored.
When SDMR is written to, signals are output to pins connected to the DDR-SDRAM according to
the table shown below.
Address bits 12 to 3 correspond to external pins M_A9 to M_A0, address bits 14 and 13 to
external pins M_BA1 and M_BA0, and address bits 18 to 15 to external pins M_A13 to M_A10.
M_CKE
n-1
n
H
H
M_CS
L
M_RAS
L
M_CAS
L
M_WE
L
Address Bit Correspondence
M_BA1 and M_A13 to M_A9 to
M_BA0
M_A10 M_A0
Bits 14 and Bits 18 to Bits 12 to
13
15
3
Rev. 1.00 Oct. 01, 2007 Page 427 of 1956
REJ09B0256-0100