SH7763 Datasheet, PDF (287/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 8 L Memory
Bit
5 to 0
Bit Name
—
Initial
Value
All 0
R/W Description
R Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.
8.2.2 L Memory Transfer Source Address Register 0 (LSA0)
When MMUCR.AT = 0 or RAMCR.RP = 0, the LSA0 specifies the transfer source physical
address for block transfer to page 0 of the L memory.
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L0SADR
Initial value : 0 0 0
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L0SADR
L0SSZ
Initial value :
00 00
R/W: R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 29 —
All 0
R Reserved
For read/write in these bits, refer General Precautions
on Handling of Product.
28 to 10 L0SADR Undefined R/W L Memory Page 0 Block Transfer Source Address
When MMUCR.AT = 0 or RAMCR.RP = 0, these bits
specify the transfer source physical address for block
transfer to page 0 in the L memory.
9 to 6 —
All 0
R Reserved
For read/write in these bits, refer to General
Precautions on Handling of Product.
Rev. 1.00 Oct. 01, 2007 Page 221 of 1956
REJ09B0256-0100