SH7763 Datasheet, PDF (1244/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Thus, the reception margin in asynchronous mode is given by formula (1).
1
| D - 0.5 |
M= (0.5 -
) - (L - 0.5) F -
(1 + F) × 100 % .................. (1)
2N
N
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
From equation (1), if F = 0 and D = 0.5, the reception margin is 46.875%, as given by formula (2).
When D = 0.5 and F = 0:
M = (0.5 – 1 / (2 × 16) ) × 100% = 46.875% ............................................... (2)
However, this is a theoretical value. A reasonable margin to allow in system designs is 20% to
30%.
(6) Reception margin and baud rate error
The 46.875% in formula (2) is the reception margin when the baud rate error is 0 (F = 0). In other
words, reception is possible even with a misalignment of approximately half a bit if there is no
reception or transmission baud rate error. If baud rate error is present in reception or transmission,
the error accumulates until the stop bit is received, reducing the reception margin.
To calculate the allowable baud rate error, formula (1) can be modified to determine the value of
F.
If D = 0.5, the result is formula (3).
F = { (15/32-M) / (L – 0.5) } × 100 (%) …… Expression (3)
Based on formula (3), the relationship between the allowable baud rate error and the reception
margin when the frame length L = 12 are as follows.
Allowable baud rate error (%) 4.07
3.64
3.20
2.33
1.46
Reception margin (%)
0
5
10
20
30
Rev. 1.00 Oct. 01, 2007 Page 1178 of 1956
REJ09B0256-0100