SH7763 Datasheet, PDF (1143/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.7 Serial Status Register (SCFSR)
SCFSR is a 16-bit register that consists of status flags that indicate the operating status of the
SCIF.
SCFSR can be read from or written to by the CPU at all times. However, 1 cannot be written to
flags ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they
must be read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be
modified.
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
        ER TEND TDFE BRK FER PER RDF DR
Initial value: 0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
R/W: R R R R R R R R R/W* R/W* R/W* R/W* R R R/W* R/W*
Note: * Only 0 can be written, to clear the flag.
Bit
15 to 8
Bit Name
—
Initial
Value
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1077 of 1956
REJ09B0256-0100